(a) Field of the Invention
The present invention relates to a display device, and an apparatus and method for driving the display device. More particularly, the present invention relates to a thin film transistor liquid crystal display (TFT-LCD), and an apparatus and method for driving the TFT-LCD.
(b) Description of the Related Art
TFT-LCDs apply an electric field to liquid crystal material having anisotropic dielectricity and injected between two substrates to form a liquid crystal layer. The two substrates are arranged substantially in parallel having a predetermined gap therebetween, and the amount of light permeating the substrates is controlled by the intensity of the electric field applied to the liquid crystal material. Because of the many advantages of the TFT-LCDxe2x80x94low power consumption, thin profile and low weight, high resolution and othersxe2x80x94the CRT, which is presently the most widely used display configuration, is being replaced by this flat panel display technology in many areas.
FIG. 1 shows a schematic view of a general TFT-LCD. The TFT-LCD includes an LCD panel 10, a gate driver 20, a data driver 30, and a timing generator 40. A plurality of gate lines G are formed on the LCD panel 10, and a plurality of data lines D are formed insulated from and crossing the gate lines G. A TFT 12 is formed in each pixel defined by the crossing of gate lines G and the data lines D. A gate electrode, source electrode, and drain electrode of each TFT 12 are connected respectively to one of the gate lines G, one of the data lines D, and a pixel electrode (not shown). Liquid crystal material is injected between a substrate (TFT substrate) on which the above elements are formed and a substrate (common electrode substrate) on which are formed common electrodes. The two substrates and the liquid crystal material injected between the two substrates act as a capacitor Cl.
The gate driver 20 applies a gate ON/OFF voltage to the gate lines G to turn the TFTs ON or OFF. The gate ON voltage is applied sequentially to one of the gate lines G such that the TFTs connected to the gate lines G are turned ON in sequence. Further, the data driver 30 applies a gray voltage to the data lines D. Finally, the timing generator 40 receives from a graphic controller (not shown) a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal CLK, and a data signal DATA, and outputs a variety of timing control signals to the gate driver 20 and the data driver 30.
The operation of the TFT-LCD structured as in the above will be described hereinafter.
The gate ON voltage is applied to the gate electrodes via the gate lines G such that the TFTs 12 are turned ON, after which the gray voltages, representing image signals, are applied to the source electrodes through the data lines D and then transmitted to the drain electrodes. As a result, the gray voltages are transmitted to the pixel electrodes, and electric fields are formed by a potential difference between the pixel electrodes and the common electrodes. An intensity of the electric field is controlled by the magnitude of the gray voltage, and the amount of light permeating the substrates is determined by this level of the electric field intensity.
As the size of the conventional TFT-LCD increases, the increased parasitic capacitance of the data lines prevents the gray voltages from sufficiently charged to the data lines. As a result, an inadequate gray voltage is transmitted to each of the pixels. To improve charge characteristics of the data lines, a method of precharging each data line to a predetermined voltage level is used in a conventional TFT-LCD.
In the conventional TFT-LCD, image data corresponding to an (n)th horizontal line (pixel line) are sampled and the sampled data are written on each of the data lines. When writing of the sampled (n)th data, image data corresponding to an (n+1)th horizontal line are sampled. Data lines are precharged in an interval between data writing times (data enable intervals) of the (n)th horizontal line and the (n+1)th horizontal line.
U.S. Pat. Nos. 5,426,447 and 5,510,807 disclose the above data line precharging methods. In these inventions, the data lines are precharged in an interval (i.e. invalid data interval) between the data enable interval of the (n)th horizontal line and the data enable interval of the (n+1)th horizontal line as described above. Also, a block addressing method is used in these inventions. In block addressing, a single pixel line is divided into blocks, each having many data lines, and each block is sequentially selected. For example, in a display device having 640 data lines, after the data lines are divided into 10 blocks each having 64 data lines, each block is selected within a single horizontal interval such that image data are written to the data lines within the selected block.
FIG. 2 shows a diagram used to describe the conventional precharging method in which precharging is performed in the interval (i.e., the invalid data interval) between the data enable intervals of the (n)th horizontal line and the (n+1)th horizontal line. A valid data interval shown in FIG. 2 refers to the interval during which sampled image data is written on one horizontal line. In the conventional precharging method, precharging is performed only between valid data intervals (data enable intervals). That is, precharging is performed during invalid data intervals P1 and P2. Accordingly, if the invalid data intervals P1 and P2 are not long enough, various problems may result.
Namely, in the conventional precharging method, since all the data lines must be precharged to a desired voltage level within the relatively short precharging interval, an extremely large amount of current is necessary for precharging, giving much stress to a current driving capability of the system. For example, in a color XGA display having 1024xc3x973 (R,G,B) data lines, if a parasitic capacitance of each data line is 80 pF, a large capacitance of 1024xc3x973xc3x9780 pF=245.7 nF must be charged within a maximum allowable time of approximately 4.6 xcexc sec to one horizontal line. Further, in the conventional precharging method, since precharging is performed in the intervals (invalid data intervals) between adjacent data enable intervals, if adjacent data intervals overlap without invalid data intervals, data lines can not be precharged.
On the other hand, a method is used in larger TFT-LCDs in which after gate blocks are selected, gate ON signals are applied to each gate line within the selected block. Such a TFT-LCD structure is disclosed in U.S. Pat. Nos. 5,028,916, 4,714,921, and 5,426,447. However, these inventions require many bus lines in a gate driver structure, increasing a circuit area of the gate drivers and resulting in line open defects during the manufacture of the gate driver.
The present invention has been made in an effort to solve the above problems.
It is an object of the present invention to provide a display device, and an apparatus and a method for driving the display device that reduce a current level needed for precharging, allowing a high degree of margin for a precharging signal generator design, and making it possible to be applied to systems having a limited valid data interval.
It is another object of the present invention to provide a display device, and an apparatus and a method for driving the display device that reduce the number of required bus lines and a circuit area of a gate driver, thereby preventing line defects.
To achieve the above objects, the present invention provides a display device (e.g., a liquid crystal display), and an apparatus and a method for driving the display device. The LCD includes an LCD panel comprising a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and a plurality of TFTs each having a gate electrode connected to one of the gate lines and a source electrode connected to one of the data lines; a gate driver for sequentially supplying gate drive signals to the gate lines to turn the TFTs ON; and a data driver that divides the data lines into an X-number of blocks, each block having a predetermined number of data lines, and that applies image signals to the data lines in an (n)th block and applies precharging voltages to the data lines in an (n+j)th block.
According to a feature of the present invention, the data driver includes a block select signal generator for generating block select signals to select one of the blocks; an image signal processor that generates the image signals for applying to the data lines in a selected block; a precharging signal generator that generates the precharging voltages for applying to the data lines in the selected block; an X-number of image signal select switch blocks for switching each of the image signals for application to one of the blocks; and an X-number of precharging select switch blocks for switching each of the precharging voltages for application to one of the blocks, wherein an (n)th block select signal simultaneously turns ON an (n)th image signal select switch block and an (n+j)th precharging signal select switch block.
According to another feature of the present invention, the precharging voltages are at a single voltage level.
According to yet another feature of the present invention, the precharging voltages have a center value between a maximum and a minimum value of the image signals.
According to still yet another feature of the present invention, an (n)th image signal select switch block among the X-number of select switch blocks comprises at least a Y-number of first MOS transistors having sources to which the image signals are applied, drains connected to the data lines, and gates to which the (n)th block select signal is applied; and wherein an (n)th precharging signal select switch block among the X-number of select switch blocks comprises at least a Y-number of second MOS transistors having sources to which the precharging voltages are applied, drains connected to the data lines, and gates to which an (nxe2x88x92j)th block select signal is applied.
According to still yet another feature of the present invention, the first and second MOS transistors are TFTs fabricated on a substrate of the LCD.
According to still yet another feature of the present invention, the TFTs are made of poly-crystal silicon or single-crystal silicon.
According to still yet another feature of the present invention, the precharging voltages each include a first precharging signal and a second precharging signal having a first voltage level and a second voltage level, respectively.
According to still yet another feature of the present invention, the first precharging signal has a predetermined value between a maximum and a center value of the image signals, and the second precharging signal has a predetermined value between a minimum value and a center value of the image signals.
According to still yet another feature of the present invention, an (n)th image signal select switch block among the X-number of select switch blocks comprises at least a Y-number of first MOS transistors having sources to which the image signals are applied, drains connected to the data lines, and gates to which the (n)th block select signal is applied; and wherein an (n)th precharging signal select switch block among the X-number of select switch blocks comprises at least a Y-number of second MOS transistors having sources to which the precharging voltages are applied, drains connected to the Y-number of data lines, and gates to which an (nxe2x88x92j)th block select signal is applied.
According to still yet another feature of the present invention, the first precharging signal is applied to the sources of the second MOS transistors connected to odd data lines, and the second precharging signal is applied to the sources of the second MOS transistors connected to even data lines.
The drive apparatus includes the gate driver and the data driver.
In another aspect, the drive apparatus is applied to a display device including a plurality of scanning lines and a plurality of data lines insulated from and intersecting the scanning lines, wherein the drive apparatus includes a scanning driver for sequentially supplying scanning signals to the scanning lines; and a data driver for dividing the data lines into an X-number of blocks, each block having a predetermined number of data lines, and applying image signals to the data lines in an (n)th block, and applying precharging voltages to the data lines in an (n+j)th block.
The method for driving an LCD includes the steps of sequentially supplying gate drive signals to the gate lines to turn the TFTs ON; and dividing the data lines into an X-number of blocks, each block having a predetermined number of data lines, and applying image signals to the data lines in an (n)th block, and applying precharging voltages to the data lines in an (n+j)th block.
According to a feature of the method, j has a value of 1.
According to another feature of the method, if the image signals are applied to data lines in a last block of an (i)th pixel row, the precharging voltages are, at the same time, applied to data lines in a first block of an (i+1)th pixel row.
According to yet another feature of the method, a first block of an (i)th pixel row uses a separate first block precharging signal received externally.
In another aspect, the LCD includes an LCD panel including an R-number of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and a plurality of TFTs each having a gate electrode connected to one of the gate lines and a source electrode connected to one of the data lines; a data driver for applying image signals to the data lines; and a gate driver for sequentially supplying gate drive signals to the gate lines to turn the TFTs ON, wherein the R-number of gate lines are divided into an X-number of blocks having a minimum Y-number of gate lines, and the X-number of blocks are divided into a minimum Z-number of groups connected to the gate driver.
The gate driver includes a group select signal generator for generating group select signals to select one of the Z-number of groups; a block select signal generator for generating block select signals to select one of the X-number of blocks; a sub-signal generator for generating sub-signals to select one of the Y-number of gate lines; and a gate array for receiving the group select signals, the block select signals, and the sub-signals, and outputting the gate drive signals.
According to another feature of the aspect, a gate array performs an AND operation of the group select signals, the block select signals, and the sub-signals.
According to yet another feature of the aspect, the gate array comprises a plurality of AND gates including input terminals connected to each of the group select signals, the block select signals, and the sub-signals, and output terminals each connected to one of the gate lines.
According to still yet another feature of the aspect, the gate array includes a plurality of NAND gates into which the group select signals, the block select signals, and the sub-signals are input; and a plurality of inverters for inverting output signals of the NAND gates and outputting the inverted signals to the gate lines.
According to still yet another feature of the aspect, the inverters include a first, second and third inverter connected to the NAND gates, of which a current drive capacity increases from the first to the third inverter.
In another aspect, the drive apparatus is applied to a display device including an R-number of scanning lines transmitting scanning signals, and a plurality of data lines transmitting image signals, the drive apparatus including a data driver for applying image signals to data lines; and a scanning driver for sequentially supplying the scanning signals to the scanning lines such that the image signals applied to the data lines are displayed, wherein the R-number of scanning lines are divided into a plurality of blocks having a maximum Y-number of the scanning lines, and the blocks are divided into a Z-number of groups having a maximum X-number of blocks.